Despite being away from his family, Vietnam local Van Loi Le continues to support his loved ones back home. How? Through Freelancer!
I need someone who is expert in academic writing and EE engineering communication and radar field and also embedded systems FPGA, the page's number will be around 50, and the topic and results and design are ready just need to be written.
We are in need of an experienced developer to help us modify existing drivers based on Java to communicate with a FPGA based Bill validator from a Raspberry pi over USB. We previously modified existing java files to communicate with a bill validator that we later found out was using an old PSD based chip, whereas the new devices are based on FPGA chips. Our old code does not communicate with these newer devices and we need help modifying the drivers to enable them to communicate. We are using a raspberry pi (raspian) to control the device. Existing Java drivers for RedHat exist and may be useful to modify for the raspberry. I have included the below files that may be useful in completing this project. Linux [url removed, login to view]: These are the existing ReHat drivers [url removed, login to view]: Install guide for redhat drivers Linux Virtual COM Port (VCP) Driver [url removed, login to view]: Guide to modify drivers for virtual com port. 002850046_Series 2000 Interface Manual: Interface manual for bill validator. [url removed, login to view]: This is a folder including Javadocs, API, Demo, and source code as well as support files. [url removed, login to view]: Similar files to the [url removed, login to view] with some differences. My expertise does not allow me to verify which is newer or more useful so I included both. [url removed, login to view]: These are the files used to develop the Java doc that controlled the older bill validator. These may be useful in understanding what the end product may look like. Connection to the device will most likely need to be done over SSH as I have the devices connected to the raspberry pi running the OS that we will be using. I will make myself avialable as often as possible to help wit testing and troubleshooting the physical hardware. Please contact me with any question as there may be details that I have left out that could be useful. thank you in advance for your help.
projekt może być oparty na chipie ADV7181
• Target DDR3 controllers development for Frame buffer (one frame delay) • Features Frame Buffer input: 1920 x 1080@60 fps, YUV 4:2:2 output: 1920 x 1080@60fps, YUV 4:2:2 • HW Platform DDR3 controller for Xilinx Zynq-7000 or 7-series FPGA • Design output Verilog DDR3 controller source codes, testbench and document
Hi, I would like to implement RSA algorithm synthesized code in Verilog up to 512 bit of encryption. - Encryption data output size can vary from 16-bit to 512 bits. - Prime number generation: two random prime number generated through LFSR and should be stored in FIFO - For every iteration different public and private key pairs should be produced. Kindly contact know if this can be done within 2 days of time frame. We can discuss about budget. Thanks, Jayesh
We need to develop a QPSK demodulator FPGA xilinx based.
We are working on nexys video board and we are trying to access DDR3 memory using IPCORE in vivado design suite software. We want to read and write data into DDR3 memory using nexys video board.
Need to design a FPGA based NMR Spectrometer for NMR Applications. Phase 1 : Interface high speed ADC and DAC with Altera FPGA and write the software for generating RF pulses and Capture Echo Signal from ADC. See the attached similar work for more details.