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    I currently have a Xilinx ISE project where I am emulating a 6522 VIA and AY-3-891x Sound Generator for a legacy sound card. See the attached project files (and datasheets if needed). The code is mostly working and well enough to achieve sound, however I believe there could be some issues with the way PWM is implemented as there seems to be distortion in the combined audio output per channel. ...

    $427 (Avg Bid)
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    Hi, I wanted to implement research work on the AES(Advnaced Encryption Standard) algorithm and differential scan attack on the same to retriever secret key. In addition, the prevention mechanism against such attack has to be developed. Coding and simulation in verilog(Xilinix-ISE/Modelsim) will be fine. Also, requires documents for the implementation (step-by-step procedure), block diagram ...

    $986 (Avg Bid)
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    VHDL task URGENT 5 days left

    Please check the attachment for the details Need to use Quartus ll

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    i want to implement three phase locked loop implemented in simulink

    $506 (Avg Bid)
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    Looking for a developer to learn and implement a real time hardware implementation of spectrum analyzer upto 100mhz bandwidth using FPGA, fast ADCs and DACs.

    $53 / hr (Avg Bid)
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    Need FPGA tutor 2 days left

    I need a tutor for fpga programming in vhdl. I have made some projects but they need to be corrected. I'm working on Xilinx Spartan-6.

    $8 / hr (Avg Bid)
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    a Q/A project about unit control system and pipelines exc. It is simple. only 3 questions. Prob take 20 minutes of someone who knows. The person also has to know MIPS Code.

    $28 (Avg Bid)
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    VHDL XILINX Lab 2 days left

    Objective: Design a coprocessor that finds square of an integer (x2), finds square-root of an integer (x0.5), converts an uppercase word to lowercase word, performs floating-point addition, and performs floating-point multiplication. Implement the design on a SoC (System on a Chip) using XPS and SDK tools of Xilinx. Requirements: (80 Points) 1. Using VHDL behavioral modeling, design a coproc...

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    Verilog and VHDL expert needed

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    hi i need someone expert professional in verilog languages to build my project i will send requirement via chat box

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    I need to implement the threshold block and verify that with two AXI VIP as you can see in the picture. I need a testbench which generates random numbers between 500 to 1000 and the threshold block count the number of data more than 500. the project can be done also with ILA but at this point I prefer system Verilog. Xilinx has a tesbecnh example which helps to write a code quickly.

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    vhdl code using xilinx and simulate it using isim 14.7

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    embedded systems Ended

    Modify the previous assignment so that, a bit string of 16 bits is sent from the UNO to the FPGA using a single data wire plus one or two control wires for synchronization (which could be either strobing or handshaking). When a pushbutton on the FPGA board is depressed and released, the FPGA sends a bit string of 16 bits to the UNO for display. Depending on the XOR result on the 16 bits, the ...

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    FPGA Project Ended

    Detail will be given in contact.

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    I have to do real time face detection on FPGA. I want someone intellectual to do it. Hardware implementation is required.

    $434 (Avg Bid)
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    SHA3 (Keccak) is fast on FPGAs: [url removed, login to view] I'm looking for the best price/performance ratio for a SHA3 implementation on FPGAs.

    $254 (Avg Bid)
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    KC705 and SD Card Ended

    I want VHDL implementation of data saving to SD card and reading it back when necessary. Main deliverables are: 1. VHDL Code using KC705 Evaluation kit. Detailed commenting must be there inside code to better understand the code. 2. Complete documentation of the code so that it can be enhanced in future. 3. Examples on how to use the code to write or read. 4. Detailed information on interface ...

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    Hi Pradeep S., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

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    VIP component development for AXI3.0 protocol with support for various features like burst type, burst size, protection, out of order, overlapping, aligned,WRAP,fixed burst . Develop BFM, Generator, Monitor, and Coverage models and also the slave model.

    $173 (Avg Bid)
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