Verilog / VHDL Jobs

Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. From 12,763 reviews, clients rate our Verilog / VHDL Designers 4.77 out of 5 stars.
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    3 jobs found, pricing in USD

    Camera should have 2 modes: One mode transfers the normal image. Another mode transfers the linescan image. Communication by ethernet to a pc computer: In normal mode... transmits normal image In linescan mode transmits linescan image The linescan mode has to get 2 lines because it has to use the bayer filter to detect colors. Then it takes those 2 lines and starts forming an image... After 4080 lines are received, it needs to convert the image to jpg and then transfer it to the computer. Requirements: Color Sensor Sensor has to have at least a resolution of 4080x2592 or a little less if we cant find one. Notes: The image sensor has to support ROI(region of interest) so the linescan mode can work.

    $561 (Avg Bid)
    $561 Avg Bid
    13 bids

    Requirement : 1. 6 input divided into 3 (2 input = 1 output) and 3 will be the output. 2 layer deep fuzzy 2. From the 3 outputs, 1 fuzzy output should be extracted which will show whether it is risk or no risk 3. 3 part model to be transferred to Simulink 4. 3 of the inputs will be in the datafile that will go to the Simulink model and the output will be in an oscilloscope 5. 2 file should be kept in which data paper or plot can be done from 2 files 6. . By combining 3 Simulink models, 3 outputs should be fitted to 1 neural network, 1 output from the neural network will be output that the patient has risk or no risk. 7. Web application should be made for deep neuro fuzzy system

    $260 (Avg Bid)
    $260 Avg Bid
    4 bids

    For 10 years, poor FPGA BTC mining implementations, completely missed the big picture with excessively large, slow, power hungry designs. Researchers presented dozens of papers on how to make this better, completely missing the mark. This is your chance to get it right. Read this paper , then and look at their Verilog here to get a good understanding about state of the art FPGA BTC mining with verilog. Then apply that to YOUR FORK of the old standard in with an updated proxy for getwork. Clues follow to make FPGA BTC mining faster, smaller, and lower power, so that you will have REAL bragging rights for the fastest, smallest, lowest power FGPA miners. Goal >10x speed up. 1) The SHA256 compression is seeded with 256 bits of very random constants and forms a large shift register as t...

    $625 (Avg Bid)
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    $625
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