Attached I have my simulation of a 32-bit RISC pipelined processor (picture also attached), and I have a few errors in the code that won't let it compile. I am trying to find someone to simply aide in the debugging process so I can continue my work, I am hoping it would be done in the next day or two.
I implemented the system that is attached in the picture, but when it came time to compile it I ran into a few errors. I want someone to help troubleshoot said errors, and then help create an assembly language program to MUL two 32-bit numbers to make a 64-bit answer within the Verilog environment to prove out the initial system. Shouldn't be complicated I'm just stuck.
Hi, You will have to generate Precision PWM of 0...40khz +/- 0.1Hz. Refer the attachment and I have tried with STM32 using HRTIM but there is 0.34hz deviation at 30002 Hz. So it doesnt meet the requirement. I request pl have a look and you need to provide the right solution and design here to achieve this.
Need someone that is deeply knowledgeable in verilog programming. Need to be ABLE to build the CPU, build memory-less, combinational components and sequential components (i.e create mux and adder's in ALU), implement 2 stage pipeline for RISC-V Processor, etc.
I want to make the interface between the sinewave function generator and FPGA kit via ADC that belong to the same kit 1. Show the result on the test - bench window 2.I Want to show the practical result on LCD screen 3. Also use the leds to show the digital value for analog value
need help with a seven segment on Nexys 4 DDR Development board
Hi, This project has a digital input and digital output. You need to design and program a FPGA for filtering the digital input and give to digital output. Get Input signal --> debounce logic --> send to output Input range (0Hz .. 1MHz) --> Output 0Hz --> 350KHz 1) when the input is on for more than 2ns , turn on the output 2) if input is off for 5ns, turn off the output 3) Output mi...
Design Specifications for the Alarm Clock ▪ Time should be displayed on the 6-digits of the 7-segment display (HHMMSS). o The left two digits will be the hour, middle two digits will display the minutes and the right two digits will display the seconds. (the period is not wired up in the DE0-CV board) o Hours will be displayed in “military time” (meaning 00 through 23). o Whenever the ...
we need Portable Pt 100 4 ch device , High Precision 0.1 accuracy with 2C communication , display with battery/5v power supply
I need to test a structural model of a sequence detector using t flip flops. I know my t equations, I have my entity and the testbench I am using to test the model. I need help constructing the structural model. It is based off a behavioral and dataflow model I already created. The software I'm using is Aldec.
I need the project A done as per the document bellow A Transimpedence/Limiting Amplifier (TIA/LA). The TIA should take the input in form of current (0.7mA -5mA) , for a current value in range should give an out put Swing of about 10mV with a bandwidth of 6.5GHz The LA should take the input from TIA and give the output swing of 200-250 mV. Simulation software Cadence will be provided and will u...
Create a circuit to do parity detection on 4 bits using Xilinix ISE, will provide complete details in the chat.