Verilog / VHDL Jobs

Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Hire Verilog / VHDL Designers

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    16 jobs found, pricing in USD

    I need a person that is good at creating circuits in Logisim.

    $32 (Avg Bid)
    $32 Avg Bid
    5 bids

    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

    $152 (Avg Bid)
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    6 bids

    Design adc data decoding module. (vivado 2018.2) Input: FCLK,DCLK,DATA_0~DATA_15.(all input signals are LVDS) Output: CLKOUT, DOUT_0 [15:0] ~ DOUT_31 [15:0]. One data path contains two adc signals. The two adc signals are distinguished by FCLK level. I need to decode the adc data into 16-bit wide data and output a total of 32 channels of adc data. The input waveform is shown in the figure. The dif...

    $214 (Avg Bid)
    $214 Avg Bid
    6 bids

    Vhdl is needed

    $27 (Avg Bid)
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    2 bids

    Need help program FPGA to communicate with TI7200 through SPI, and generate 300 and 100 Hz sine waves to drive two electric coils,

    $504 (Avg Bid)
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    13 bids

    Use a Verilog and Do exactly what is on the paper and hand me a report with codes, synthesized diagrams, and a description comparing the different state assignments

    $22 (Avg Bid)
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    4 bids
    VHDL questions 2 days left

    I have some VHDL questions which I nedd to be solved .

    $19 (Avg Bid)
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    5 bids
    FPGA Designing 2 days left

    Hello, I need FPGA designing expert. I have complete details of the project. Place your bids, i will share the details with the best bidder. Thank you in advance

    $59 (Avg Bid)
    $59 Avg Bid
    14 bids

    build a matlab simulation of pmu without time stamping for 1 phase use recursive algorithm for [login to view URL] each sub system like adc etc

    $49 (Avg Bid)
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    6 bids

    My aim of this work is to see how it would be done from a different point of view. What I would like to be done is: * Check the Simulink model to see if that's done correctly. * Finish minimum resource version in filter bank Simulink model (just add memory and switch between memory in each cycle and do DFT). * Implement the minimum resource filter bank in VHDL in the simplest possible way. I...

    $236 (Avg Bid)
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    9 bids
    PLL in VHDL 1 day left
    VERIFIED

    Add in our Design a PLL for variable clock speed

    $173 (Avg Bid)
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    12 bids

    The main aim of the project is to design and simulate a Blackjack game model using VHDL and demonstrate it using Alter Cyclone V SoC. The inputs are taken from the player using the switches and push buttons while the output is displayed on the 7-segment display of the FPGA.

    $372 (Avg Bid)
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    3 bids
    Logic circuit 10 hours left

    Simulate traffic lights with three colors (red, yellow, green) alternating at given intervals using only following elements: multi-input AND/OR/XOR gates, D Flip-Flops, Clock, input/output pins, LED lights. Time delays for red, yellow and green colors should correspond to some three digits of your student ID (if there is 0, change it with another digit).

    $26 (Avg Bid)
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    13 bids

    1. Design platform: VIVADO 18.2 2. Chip: xcz7020CLG484-1 3. language: Verilog 4. Input is all lvds, fclk is frame clockwise, DCLK is data clock, DDR mode Data receives 16 pairs of ADC data. A pair of LVDS DATA inputs 2 channels of ADC data. FCLK is channel A data when it is high and channel B data when it is low. Output data with 32 channel bit width of 12

    $186 (Avg Bid)
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    8 bids
    Diseño FPGAs en VHDL 3 days left
    VERIFIED

    Proyecto enfocado al diseño VHDL sobre FPGAS. Desarrollo de código y de bancos de pruebas, verificación del funcionamiento y resolución de algunas cuestiones. Tiene que estar terminado para el día 17 de diciembre. Se adjunta toda la descripción de lo que hay que hacer, así como unas plantillas para las soluciones y algunos bancos de pruebas.

    $33 (Avg Bid)
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    1 bids
    Trophy icon VHDL Design 2 days left

    Concurso enfocado al diseño VHDL sobre FPGAS. Desarrollo de código y de bancos de pruebas, verificación del funcionamiento y resolución de algunas cuestiones. El concurso comienza hoy y termina en 7 días. Los participantes tienen una semana para avanzar todo lo que puedan. El participante ganador dispondrá de 10 días más para finalizar ...

    $34 (Avg Bid)
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    1 entries