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Standard cells and 16 bit carry look a head adder Using X2GO

$30-250 USD

Completed
Posted over 5 years ago

$30-250 USD

Paid on delivery
Details will provide later
Project ID: 18075857

About the project

3 proposals
Remote project
Active 5 yrs ago

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Hi, as per discussed in chat. Will complete the work mentioned by Sunday midnight PST. Will deliver a clean work on time.
$222 USD in 3 days
0.0 (0 reviews)
2.9
2.9
3 freelancers are bidding on average $207 USD for this job
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Dear sir I have more than 10 years experience in digital design using verilog and vhdl please check my profile page also please message me so that we can discuss Best regards
$200 USD in 1 day
4.9 (473 reviews)
8.0
8.0
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I have long experience with FPGA and VHDL . I work with both intel and Xilinx FPGAs , SoC and SOPC. I use Quartus II and Vivado IDEs accordingly. I test timing compliance through timing analysis . I deliver tested , neat and well-commented code that can be reused or modified for future development. More to be discussed once you contact me . BR, M.T.
$200 USD in 3 days
4.8 (33 reviews)
5.8
5.8

About the client

Flag of UNITED STATES
Miami, United States
5.0
4
Payment method verified
Member since Nov 7, 2017

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