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Implement RSA algorithm synthesized code (512 bit) in Verilog

₹600-1500 INR

Closed
Posted about 6 years ago

₹600-1500 INR

Paid on delivery
Hi, I would like to implement RSA algorithm synthesized code in Verilog up to 512 bit of encryption. - Encryption data output size can vary from 16-bit to 512 bits. - Prime number generation: two random prime number generated through LFSR and should be stored in FIFO - For every iteration different public and private key pairs should be produced. Kindly contact know if this can be done within 2 days of time frame. We can discuss about budget. Thanks, Jayesh
Project ID: 16362243

About the project

9 proposals
Remote project
Active 6 yrs ago

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9 freelancers are bidding on average ₹6,964 INR for this job
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A proposal has not yet been provided
₹27,777 INR in 2 days
5.0 (313 reviews)
7.6
7.6
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₹600 INR in 3 days
5.0 (54 reviews)
5.8
5.8
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A proposal has not yet been provided
₹11,111 INR in 14 days
0.0 (0 reviews)
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I am an experienced RTL designer in one of the product companies. I have good experience in building complex digital systems. Pls. consider my bud.
₹1,300 INR in 2 days
0.0 (0 reviews)
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Hey, I have an experience in cryptography and it seems doable in two days so please contact me for more details.
₹4,444 INR in 2 days
0.0 (0 reviews)
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I could locate 4h per day to work on this project. expert on Verilog design & FPGA. Available platform for testing & simualtion. Relevant Skills and Experience worked in large company, expertise in Verilog design for GPU/Ethernet, also implement FPGA system for 25Gs Ethernet
₹2,250 INR in 2 days
0.0 (0 reviews)
0.0
0.0
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I am an expert in digital design let me do it
₹750 INR in 2 days
0.0 (0 reviews)
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I work in system verilog and c++ in my daily job. So I can assure u to code in system verilog. Also i can explain u and giv some suggestions.
₹2,777 INR in 1 day
0.0 (0 reviews)
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Member since Nov 19, 2017

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