Single clock process design based on RISC-V ISA
₹600-1500 INR
Paid on delivery
I am looking for a freelancer to design a single clock process based on RISC-V ISA using Verilog. The clock process design must have the following specific features and functionalities:
The project only requires the implementation of the base RISC-V ISA, without any specific extensions. The ideal freelancer must be skilled and experienced in Verilog and have a deep understanding of RISC-V ISA. Additionally, I would prefer someone who has previously worked on similar projects and can provide examples of their work.
Project ID: #36520046
About the project
2 freelancers are bidding on average ₹900 for this job
I wm an. Rtl design engineer with 3+ years of experience. I have experience in fpga design, sta, verilog.