Single clock process design based on RISC-V ISA

Closed Posted 10 months ago Paid on delivery
Closed Paid on delivery

I am looking for a freelancer to design a single clock process based on RISC-V ISA using Verilog. The clock process design must have the following specific features and functionalities:

The project only requires the implementation of the base RISC-V ISA, without any specific extensions. The ideal freelancer must be skilled and experienced in Verilog and have a deep understanding of RISC-V ISA. Additionally, I would prefer someone who has previously worked on similar projects and can provide examples of their work.

Verilog / VHDL FPGA Engineering Electronics Electrical Engineering

Project ID: #36520046

About the project

2 proposals Remote project Active 9 mos ago

2 freelancers are bidding on average ₹900 for this job

hadyghata

Dear Sir, I have been teaching the RISC-V ISA to students for four years now at the AUC. The course I reached contain a very similar project that require the students to implement the RV32I ( Base Integer Instruction More

₹600 INR in 6 days
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psirisha2023

I wm an. Rtl design engineer with 3+ years of experience. I have experience in fpga design, sta, verilog.

₹1200 INR in 7 days
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