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    2,000 fpga project jobs found, pricing in USD
    Sensing Position Ended

    Need to localize indoor position for multiple people using uwb tag and also need to use fpga

    Arduino Electrical Engineering Electronics Microcontroller Python
    $148 (Avg Bid)
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    Embedded C Developer Needed Ended

    ...and drop down menus · Hands-on experience on various microcontrollers AVR/PIC/ARM/STM32F4/Xilinx XC7Z020 · IDE experiences on AVR Studio/ MPLAB/Keil IDE · Peripherals like - UART/SPI/I2C/ADC/PWM FPGA interfacing includes C Code for: ADC IC with SPI interface. DAC IC with SPI interface. 12 Bit Parallel Data interface with DAC IC. 8 Bit Parallel Data interface with DAC IC for sine wave generation. 10 PWM channel interface. SDRAM interface. SD Card Interface. USB interface RS232 Interface Current Steering DAC interface interaction experience on FPGA Able to prepare and implement the Pre-production plans like Bill of material preparation, Assembly instructions and final quality testing procedures. ...

    Arduino C Programming C++ Programming Electronics Microcontroller
    $726 (Avg Bid)
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    Project XYZ in Space Industry Ended

    Embedded Linux with FPGA capability. From VHDL to application level programming.

    C Programming C++ Programming FPGA Linux Verilog / VHDL
    $42 / hr (Avg Bid)
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    Technical expert (Xilinx Vivado) Ended

    We are Hiring Technical expert (Xilinx Vivado) Position: Academic Technical expert Freelancer Experience: 2+ years Qualification: Masters or Doctorate in Electronics & Communication Engineering Skills Required: Turbo Decoder VLSI Xilinx Vivado FPGA Verilog Machine learning Specific area: Need a Verilog, Xilinx Vivado and Machine learning expert Time: Part-time/Freelance Job Description: Require a Freelancer, who can do coding will be done on Xilinx Vivado. Implementation will be done on FPGA using Verilog/ system Verilog language

    FPGA Machine Learning (ML) Verilog / VHDL Very-large-scale integration (VLSI)
    $315 (Avg Bid)
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    implement openwifi on fpga zynq AX7020 Ended

    I am searching for an individual who possesses strong expertise in FPGA and Zynq AX7020 IC, specifically to assist me in installing OpenWiFi on my FPGA. All necessary information and resources are available on Github. The ideal candidate should be highly experienced in installing OpenWiFi and familiar with both FPGA and Zynq AX7020 IC. They should be able to provide clear guidance and instructions on the installation process. This project is critical to me, and I need someone reliable and highly skilled who can deliver quality results. If you have the necessary expertise and skills to help me with this project, please get in touch. I'm looking forward to hearing from you.

    Electronics FPGA Linux Verilog / VHDL
    $10 (Avg Bid)
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    SoC FPGA developer Ended

    Looking for FPGA Developer who has experience in VHDL on SoC FPGA architecture

    FPGA FPGA Coding Verilog / VHDL
    $143 (Avg Bid)
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    LIN Bus controller FPGA Ended

    I’m looking for a talented freelancer to help me design a LIN Bus controller FPGA, in VHDL. To be considered for the job, candidates should include past work in their application and provide relevant experience related to this project. Any working code previously developed is a plus. Deadline for the delivery 20th April 2023. A quotation is required, together with the proof of previous expertise of the working code already developed It will be required to 1. deliver VHDL source code for LIN master bus controller 2. testbench with a Verification module, or any other sort of mechanism to emulate a node 3. Integration and testing of a simple test code on hardware provided by us 4. documentation

    Automotive Electronics FPGA Verilog / VHDL
    $1310 (Avg Bid)
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    SOC technology porting engineer Ended

    Europe, Italy timezone preferred. Lead the activity for porting FPGA design to Silicon technology (memory replacement, ...) Carry on simulations of the updated RTL design to check that the functionality remains unchanged Execute static and formal verification of RTL code using appropriate tools Run trial synthesis on the RTL design and check the timing violations Lead the activities for SoC sub-block Static Timing Analysis. Required Skills (expert): VHDL language Digital ASIC design flow Use of digital simulations with standard industry simulators (Mentor QuestaCore) Static and formal RTL verification (e.g. Synopsys Spyglass) Synthesis tools (e.g. Cadence Genus) UVM and System Verilog test benches

    ASIC Electrical Engineering Electronics Verilog / VHDL
    $20 - $40 / hr
    Sealed NDA
    $20 - $40 / hr
    8 bids
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    Spartan 3E Image processing Ended

    Hello! I got a task at college to use the FPGA Spartan 3E board for image processing. The image data is written into the FPGA, and then the image is processed by adding an effect, such as blur, darken, or something similar. The user selects a specific switch to choose which effect to apply. The processed image data is returned to the computer, and this data can be converted to BMP format to see the final result. It would be desirable to use the UART protocol. I am willing to pay $120 for this project. If you are interested, please let me know and we can discuss the details. Thank you :)

    FPGA Image Processing Verilog / VHDL
    $149 (Avg Bid)
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    Sound Detection Sensor to turn on LED on FPGA DE1 SoC Board Cyclone V Ended

    Hi, can you help me out to code Verilog coding for the sound detection sensor for turning on the LED on DE1 SoC Cyclone V board?

    Arduino Electrical Engineering FPGA Microcontroller Verilog / VHDL
    $25 (Avg Bid)
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    antenna and beamforming design for 5G Ended

    design beamforming antenna using standard algorithms in x86, FPGA. RF engineering and radar, 5G Output will be working algorithm and prototype of beamforming in 5ghz - 12ghz x-band range

    Antenna Design Electrical Engineering Electronics FPGA Power Amplifier RF RADAR/LIDAR Radio Frequency Verilog / VHDL Wireless Radio Frequency Engineering
    $13017 (Avg Bid)
    Featured NDA
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    PPG signals using sensor on ARTIX-7 FPGA (NEXYS-A7) with Machine learning training - 19/02/2023 13:39 EST Ended

    ... 1) CNN to predict Blood pressure from PPG on Nexys A7 FPGA. 2) input to FPGA should be analog PPG signal. 3) output should be SBP and DBP values which has to be displayed on LCDof ARTIX-7. 4) Training and testing of CNN should be done using python. 5) A report describing the system and it's operation with all the codes. Certain Points for More Clarification: 1) the CNN should be "1-D CNN" and the database should be kaggle database. 2) python file for training and predicting BP values. 3) vivado hlx for CNN with weights from the above mentioned python training. 4) simulation from vivado for CNN and printing BP values with accuracy greater than 95%. 5) implement CNN thus created on Nexys A7 100T FPGA board with "...

    Deep Learning Electronics FPGA Machine Learning (ML) Microcontroller
    $191 (Avg Bid)
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    FPGA and Microconroller Ended

    I want someone to design using FPGA and Microcontroller

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    $133 (Avg Bid)
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    34 bids
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    altium 365 Pro who has experience in Zynq ultrasclae+ MPSoc FPGA design and AD9361 RF receiver Ended

    I am looking for an experienced Altium PCB design who has worked on complex PCB design using Altium 365. - Zynq ultrasclae+ MPSoc FPGA - AD9361 - AD9371 I only need individual freelancer. Full-time available can work on US time zone should reply ASAP. Please share your portfolios what you have done in similar fields.

    Circuit Design Electrical Engineering Electronics Microcontroller PCB Layout
    $23 / hr (Avg Bid)
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    Design and Simulation of Combinatorial and Sequential Digital Systems Using VHDL Behavioral Modeling and the Xilinx Vivado Design Suite Ended

    ...configure the radix of outputs as “binary”. 3) Create an XDC file to map your circuit IOs to the Basys3 board. Use slide switches for the 4-bit input data operands, carry in, and functionality mode selection bits (S2-S0). Use LEDs to display the outputs: result and carry out. 4) Synthesize and implement your design in Vivado, then generate bit stream & program the FPGA board. 5) Test and verify the operation of your design on the FPGA board for all arithmetic & logical operations using a subset of input data patterns you choose from the functional table....

    C Programming C++ Programming Electronics Microcontroller Verilog / VHDL
    $68 (Avg Bid)
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    FPGA Programmer Ended

    We are looking for a FPGA programmer who can debug the code for FPGA circuit and code the FPGA accordingly. I have few details that all I have. Please review the files attached before placing the bids.

    Electrical Engineering Electronics Engineering FPGA Verilog / VHDL
    $43 (Avg Bid)
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    DSP chip fast proccesing and curve fitting on fast signal. Ended

    Need somebody who has done procesing of signals in realtime with some DSP chip that is fast enough, and within normal consumer budget. Or FPGA, or whatever hardware configurations, that are available. The attached spike has a duration of aprox 7 microseconds and an amplitude of 0.1 to 5.5 V. The input of the spike is around 200hz. We are trying to push it to 500hz or more. I need sampling on each channel at least 7msps. The proccesing each sample set and curve fitting, to get the peak perfect precision mathematical peak with a precision of 2 miliVolts. Then the data is interpreted in order to maintain the Curve, and not get saturated, (with that triangle-ish shape img6303) and a control signal is emitted to lower the excitation and come back to the curve normal shape. These...

    Digital Signal Processing Electrical Engineering Electronics Microcontroller Signal Processing
    $421 (Avg Bid)
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    debug FPGA program - Cyclone Altera chip Ended

    I have a board i need to fix for an equipment in my store. Looking for an FPGA expert that can debug the program files i got from the manufacturer. I was told this should be simple for someone that knows what they are doing.

    Arduino Electronics FPGA Microcontroller Verilog / VHDL
    $151 (Avg Bid)
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    Private project or contest #35886334 Ended

    Please Sign Up or Login to see details.

    FPGA Verilog / VHDL
    Urgent
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    Fpga based skin cancer detection system using GAN Ended

    Devlop a model to detect skin cancer using conditional GAN translation and apply on cnn models. Execute the model on fpga processor

    FPGA Image Processing Matlab and Mathematica Python Verilog / VHDL
    $325 (Avg Bid)
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    Understanding of FPGA for a report Ended

    I want someone who understands FPGA, Vivado, Verilog, VHDL etc for a report

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    $73 (Avg Bid)
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    QPSK based digital communication Ended

    QPSK modulation and demodulation with Turbo Encoder/Decoder, Interlever, Channel Estimator, Channel Equalizer, Pulse shaping filter, coarse and fine synchronization etc. Defined Parameters: Data Rate: 16kbps, 100kbps, 2msps Modulation Scheme: QPSK Bandwidth: 25KHz, 300KHz, 2MHz Sampling Rate: Twice of Data Rate Software: Vivado 2019.1 (for hardware design d...Channel Equalizer, Pulse shaping filter, coarse and fine synchronization etc. Defined Parameters: Data Rate: 16kbps, 100kbps, 2msps Modulation Scheme: QPSK Bandwidth: 25KHz, 300KHz, 2MHz Sampling Rate: Twice of Data Rate Software: Vivado 2019.1 (for hardware design development) on Zynq 7035 and 7030. Linux Based OS to make Linux OS executable files. Hardware: Zynq 7030 and 7035 FPGA and AD9361 Tr...

    Communications Digital Design Digital Signal Processing FPGA Linux Telecommunications Engineering Verilog / VHDL Wireless Wireless Radio Frequency Engineering
    $6181 (Avg Bid)
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    Connecting sensor with lattice FPGA Ended

    To interface lattice FPGA with ultrasonic sensor (5 )and lidar sensor(4) with the provision for connecting an MIPI based camera module (no AI stuffs),the FPGA would be connected to stm32h7 via SPI interface . More details via chat including the sensor type

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    $157 (Avg Bid)
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    Mining Pool Ended

    ...mining pool. To be clear I am not looking for a replica of any existing open source pools that currently exist however, the source code can be used from such open source code to create this new pool with the full understanding that the code must be fully tested for bugs and security holes. Emphasis on secure. 100% SOURCE CODE MUST BE MADE AVAILABLE DURING THIS ENTIRE PROJECT Key targets that must be met during this project are: 1. Continued development must be factored in. This is a long term partnership not a one off job. 2. Source code must be made available for 3rd party security audits and verification. 3. The Pool must run on the most recent versions of Ubuntu. 4. Miners must be able to use all types of Bitcoin Addresses from Legacy, Segwit to taproot... 5. Stratum...

    Blockchain JavaScript Node.js React.js Web3.js
    $479 (Avg Bid)
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    looking for FPGA developer Ended

    Looking for FPGA developer to write simple program on Intel Stratix board

    Arduino Electronics FPGA Microcontroller Verilog / VHDL
    $113 (Avg Bid)
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    Intel MAX 10 FPGA PROJECT Ended

    completing design demonstration of work and explanation Report and final work -this includes all the recording of work -how and why

    Analog Electronics Digital Electronics FPGA FPGA Coding Verilog / VHDL
    $110 (Avg Bid)
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    Fpga based skin cancer detection system Ended

    Devlop a model to detec skin cancer

    FPGA Image Processing Matlab and Mathematica Python Verilog / VHDL
    $335 (Avg Bid)
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    I have multiple tasks for Electrical Engineers Ended

    Hi, How are you doing. I am looking for electrical engineers to work on multiple tasks in following areas: • Embedded C Programming. • VHDL/Verilog, LABView/ Multisim/PSPICE • Network Simulator NS2/NS3 • Microcontroller like Arduino, Raspberry Pi, FPGA, AVR, PIC and STM32. • IDEs like Keil MDK V5, ATmel studio and MPLab XC8. • PLCs / SCADA • PCB Designing-Proteus, Eagle. • IOT Technologies like Ethernet, GSM GPRS. • HTTP Restful APIs connection for IOT Communications. I am looking for long term work relationship. New freelancers are warmly welcomed. Important Note: I need dedicated freelancers who strictly follow the deadline and give me good quality work without any plagiarism.

    C Programming Electrical Engineering Electronics Microcontroller Verilog / VHDL
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    PCB Design / Layout Ended

    Looking for an experienced designer / electrical engineer to move further with our products. We currently have 4 projects that involve ESP32, FPGA and MPUs. We're hoping to find someone who will be able to work on our other projects after completion of the first one. This particular project involves a 4 single layer board design using ESP32, solar power management, super capacitors and SPI display. We're looking for someone who is able to complete the project based on the requirements and is able to provide consultation on the future designs.

    Circuit Design Electrical Engineering Electronics Microcontroller PCB Layout
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    AD9361+ FPGA interface and code modifications Ended

    Hello,I am looking for guys who could integrate the AD9361 with lattice FPGA series and also port some of the codes which were made fro the xilinx FPGA into the same lattice FPGA.

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    $172 (Avg Bid)
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    Implementation of Gradient Descent Optimization Algorithms on FPGA in Verilog language which is synthesizable. Ended

    Hi Moaz Khaled Feriz K., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

    Altera Quartus ASIC Digital ASIC Coding FPGA Verilog / VHDL
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    FPGA/Microcontroller programming for hardware control Ended

    We have a need for a programmer for both microcontrollers and FPGAs to control I/O from a host computer to custom high channel count, high voltage drive electronics used to control deformable mirrors.

    C++ Programming Electrical Engineering FPGA Microcontroller
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    fpga video processing pipeline. -- 2 Ended

    accept digital RGB input (24bit + HS VS DE) in one resolution, output digital RGB output (24bit + HS VS DE) in another resolution. Features required : 1. optional de-interlacer (swit...source code. Must include verilog testbench that will accept input picture(in any format) and produce resulting picture(in any format). suggested pipeline i/o ports: Sysclk, [23:0] RGBin, HSin,VSin,DEin, Clkin [23:0] RGBout, HSout, VSout, DEout, Clkout [31:0] parameters[0:...] (whatever count is required). all needed memory interfaces signals to the memory multiplexer. Any dev board and any FPGA device can be used for testing it on. It is essential that the potential developer will provide the samples (with code fragments) of previous experience. More than 3 years of Verliog/ HDL experience ...

    Electronics FPGA Verilog / VHDL
    $2000 (Avg Bid)
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    SE-1 GUI rev 1 Ended

    We need to develop a GUI in a preact framework, using Javascript, interfacing to an FPGA via a FTDI chip over USB. I uploaded the mock up code we have running, showing some details in what we have thought. Base code is to be in GO.

    FPGA FPGA Coding Golang Graphical User Interface (GUI) JavaScript Software Architecture Software Development Software Engineering System Admin System Administration Systems Engineering
    $37 / hr (Avg Bid)
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    Expert on VHDL and FPGA (only expert required) -- 2 Ended

    I am looking to hire an individual who really understand this subject. should be able to solve any problems related to this subject. communicate and be able to write good programming and simulation designs.

    Electrical Engineering Engineering FPGA Matlab and Mathematica Verilog / VHDL
    $140 (Avg Bid)
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    Verilog project for image de-hazing (using dark channel prior algorithm) Ended

    The objective is to create a verilog code for image dehazing. The image is converted into a text file using Matlab(all pixel values are converted into corresponding hexadecimal values). This text file is given as the input to the verilog program. First we need to find the minimum of RGB value of each pixel and create a matrix. Then we need to consider a small window/mask in the new m...the entire new matrix to create the darkchannel image. Then by using the equations using the darkchannel prior algorithm we need to recreate a haze free image. (the output of the verilog code will be a text file and is recreated into an image using Matlab. I am attaching a reference paper. I just need to get the basic dehazing part from it. #verilog #matlab #imageprocessing #darkchannelprior #fpga...

    Electrical Engineering FPGA FPGA Coding Image Processing Verilog / VHDL
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    line following bot Ended

    I need code for my bot who follow the given line using line sensor. this code should be written in verilog language and fpga cyclone 4 is used as board.

    FPGA FPGA Coding Microcontroller Verilog / VHDL
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    FPGA Engineer Ended

    We are in the need of FPGA Engineer for a SDR product. We want to maximize the Power Output of SDR (Software Defined Radio) with the use of Amplifiers. You can have remote access to customize the FPGA of the SDR + Amplifiers. Currently we have them already operational - however, we know that we need to tweak more to maximize this. No need to fully re-write the FPGA coding - it is truly tweaking the code based upon Technical Git / Manual information. Budget 500 - 750.

    Electrical Engineering FPGA Microcontroller Power Amplifier RF Verilog / VHDL
    $537 (Avg Bid)
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    Real-time object detection using FPGA Ended

    Input(Live video) is accessed from the camera connected to the board and output should be displayed in the monitor connected to the FPGA board. and output should have a bounding box with a label of the detected object.

    FPGA Matlab and Mathematica Verilog / VHDL
    $178 (Avg Bid)
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    XTEA Light Encryption-Decryption Engine Ended

    In this project students are asked to implement a an XTEA Encryption/Decryption VHDL Engine, implemented in both C code and VHDL code. It supposed to be built as a custom hardware module and be interfaced to the NIOS II soft processor in the Alter- Intel Cyclone V FPGA chip [De-10Nano board]. The HDL code implements 2 number of pins: first an input from stdr_logic_vector type form of 32-bit length, and second an output with 32-bit of the same type. The Key is 32-bit in length, and they must be stored inside the VHDL code. The input reception and output generation may take multiple clock cycles or states but could be designed in less than that if was applicable. The internet could be surfed to lookup codes for both C and VHDL but the group is responsible to convert and modify ...

    C Programming C++ Programming Electronics Microcontroller Verilog / VHDL
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    FPGA system Ended

    Hi I need a expert in red pitaya.I want to design project using red pitaya

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
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    Vhdl for video processing FPGA Ended

    We need a VHDL designer with expertise on video processing codec.

    Engineering FPGA Verilog / VHDL Video Processing
    $32 / hr (Avg Bid)
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    TCL script for FPGA design flow automation Ended

    We need a script to automate our FPGA design flow. Preferred in tcl language 1. Set the environment 2. Grab sources from repo 3. Run simulation and regression test 4. Run synthesis and place and route (vendor independent) 5. Generate reports 6. More than one project, we want to run it during night time

    FPGA Git Scripting Test Automation
    $650 (Avg Bid)
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    FPGA design support Ended

    the company needs FPGA design services support for a multichannel DMA systes

    FPGA Verilog / VHDL
    $40 / hr (Avg Bid)
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    IIC Not Working Properly on Xilinx Artix FPGA Ended

    I need to use Xilinx IIC IP on Artix board as a master, I used it in master mode and it didn't work well (The generated signal seems to be random) I tried the IP on Zynq platform and it worked well, but on Artix it beahves inproperly! I need someone to get it up and running on my chip.

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
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    FPGA Expert Ended

    Xilinx ZCU104 MPSOC FPGA Expert

    FPGA Coding Linux MPSoC Design UNIX
    $52 / hr (Avg Bid)
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    I need a Verilog/Vivado expert Ended

    Im working on a Simon Says project that needs to be implemented on a Xillinx FPGA. It alsof includes memory, FSM

    Electronics FPGA Microcontroller Verilog / VHDL
    $39 (Avg Bid)
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    I need a Verilog/Vivado expert -- 2 Ended

    Im working on a Simon Says project that needs to be implemented on a Xillinx FPGA. It alsof includes memory, FSM

    Electronics FPGA Microcontroller Verilog / VHDL
    $37 (Avg Bid)
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    FPGA Implementation of Lightweight Security Mechanisms SIMON & SPECK -- 2 Ended

    Objectives of this project are Benchmarking speed, ROM, and RAM usage of software implementations of Simon and Speck's ciphers using C++ and XILINX to improve the performance of SIMON and SPECK on ASICs, FPGAs, microcontrollers, and microprocessors. - Memory benchmarking via C code - Slice count benchmarking via FPGA - Gate equivalent benchmarking via ASIC Implementation

    C++ Programming Electrical Engineering Electronics Embedded Systems FPGA Coding
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    Fpga setup Ended

    We are a high frequency trading startup based out of India and we are looking to setup an fpga based trading infrastructure

    FPGA Verilog / VHDL
    $550 (Avg Bid)
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