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PAL/NTSC video is samples at 27 MHz @ 10 bits and stored in a circular buffer, buffer does have a length of two video lines (128us). The video is simply processed and send out to a DAC back into normal PAL/NTSC. FPGA used is XC3S50AN. Your required to write the VHDL Code for the FPGA used. Video Codec used is ADV7202 from Analog devices. Control processor from Microchip is communicating with the FPGA for sending commands (type of processing needed). More details will be given to the winner of the Bid.

This project calls to program an FPGA or MCU based solution (Figure 1 at enclosed document). Provider/Coder/seller to provide a working prototype, optional large volume (10K, 50K, 100K) tested board (board = “Solution Packaging“) supporting: Parallel (“Host-side??) to Parallel-IDE and USB (Target-side) adapter with configuration and control registers at Host-side. These registers will also control the a small 256KB RAM (at FPGA or MCU), Boot_Block access, etc **(see enclosed updated document). **This is an embedded project and coder must have schematic-H/W and code (S/W and optionally VHDL) expertise. Remark: This was a 4 phase project and hereby the first to show: Phase-1 project. Former bidders requsted to place a bid per all four phases. This bid call...

**General Description** This project calls to program an FPGA or MCU based solution (Figure 1 at enclosed document). Provider/Coder/seller to provide a working prototype, optional large volume (10K, 50K, 100K) tested board (board = “Solution Packaging“) supporting: Parallel (“Host-side??) to Parallel-IDE and USB (Target-side) adapter with configuration and control registers at Host-side. These registers will also control the a small 256KB RAM (at FPGA or MCU), Boot_Block access, etc (see enclosed document). This is an embedded project and coder must have schematic-H/W and code (S/W and optionally VHDL) expertise. Remark: This is a 4 phase project. Coder requsted to place a bid per each phase. ## Deliverables 1) Complete and fully-functional working p...

Digital Engineer, FPGA/VHDL/C++, can result in shared ownership of the project. An ongoing hardware development project needs personnel for debugging/completing a design based on FPGA. Job Description Work as a VHDL developer on a hardware development team to complete a leading edge development project building next generation network security systems. Candidates shall meet following qualifications: Good general programming skills Working VHDL knowledge Working C/C++ knowledge GNU tools knowledge Good understanding of computer architecture About Us Inproa Data AB is a Swedish company working with data security and recovery. We have been in this business for over seventeen years. Our methods for data recovery and security belong to the most advanced ...

...personnel for debugging/completing a design based on FPGA.** **Job Description** Work as a VHDL developer to completing a design based on FPGA. ## Deliverables Candidates shall meet following qualifications: **Xilinx FPGA devices and design toolsets. ****FPGA code design using the VHDL language. Strong architectural design skills. ** Working VHDL knowledge Working C/C++ knowledge GNU tools knowledge Code simulation and verification using a variety of development toolsets. **About Us** Inproa Data AB is a Swedish company working with data security and recovery. We have been in this business for over seventeen years. Our methods for data recovery and security belong to the most advanced in the world. ## Platform FPGA...

We require porting of a design which uses 3 Cyclone FPGAs into one Cyclone3 FPGA, source code for the firmware is available for the coder, knowledge of VHDL/Verilog along with hardware level cyclone3 knowledge required.

Linux Client/Server System where Linux is the X-client and Thin Clients are X-servers. Linux preferred distro would be Gentoo but others possible. System should be packed in self booting iso file. ## Deliverables Client/Server System Server x86 based Linux (prefer Gentoo but other L...password set individual user rights admin teacher student guest Control Panel install /remove program add/delete/change user account ldap help function individual internet access control for each user allow prohibit filter backup ask which media USB HDD SATA external SATA DVD daily (time) now show active users stop user show processes stop process Client x86 based PXE Net-booting X-Server USB VoIP FPGA Client probably RDP Client (will get specs later and can put sample at programers...

...SD card or USB key. 6. Ethernet 10/100/1000 connectivity. 7. Reads DVD/CD/BD drive. Determines disc format and the best way to copy. 8. We can provide example source code from PC on how to handle each media format. Source code is for reference only. 9. Possible support for up to 14 drives. More than one FPGA or CPLD can be used. SEE FEATURE LIST. ## Deliverables 1. PCB Design 2. Schematics 3. Functional Prototype 4. Source code for FPGA 5. Source code for any processors 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other ...

I have a server that receives calls from people trying to automate their houses.? The commands are stored for each user on the server. Right now, we have a pc-based application that checks a url periodically. The java application "wakes" up, checks the url, and sends commands to the serial port based on the received command. (The serial port uses the x10 command set) Two problems with this that we've encountered: 1) No one wants to leave their computer on all the time. 2) Not all computers have a serial port. So, the idea is to bundle this application up into? a chip with an ethernet plug, and a serial port,? and maybe some switches for settings. The idea is to have a standalone chip that can do this process? independent of a pc. I hope this helps exp...

...picture: I have a sequence of "home automation" commands on a web server? that need to be? transmitted to? several in-home? devices in multiple locations. I need a standalone device that can receive these commands and transmit the commands over the serial port. Here is the serial port protocol to follow: <> Details: ? This may be an fpga project with serial and ethernet connectors, or maybe we can use one the following products:? <> Basically I need help setting one of these up or developing something custom. I need to know how to pass commands to these

...picture: I have a sequence of "home automation" commands on a web server? that need to be? transmitted to? several in-home? devices in multiple locations. I need a standalone device that can receive these commands and transmit the commands over the serial port. Here is the serial port protocol to follow: <> Details: ? This may be an fpga project with serial and ethernet connectors, or maybe we can use one the following products:? <> Basically I need help setting one of these up or developing something custom. I need to know how to pass commands to these

Hi everyone, I have project, Division by repeated Multiplication, the project is implement the Division by repeated multiplication algorithm in VHDL (IN STRUCTURAL CODE, NOT JUST BEHAVIORAL CODE). since I was running out of time, if there's anyone out there has been mastering on this or ever did this kind of project please help me. I will be s...algorithm in VHDL (IN STRUCTURAL CODE, NOT JUST BEHAVIORAL CODE). since I was running out of time, if there's anyone out there has been mastering on this or ever did this kind of project please help me. I will be so very thankfull by this. really. looking forward to your helps... Thanks, Regards, Steve. PS. I need the final code including the testbench and the syntesis result on the general purpose fpga (in terms of area, delay and...

1.? ? ? ? ? ? The thing that is holding me back is a software guy who knows cars. I need someone who knows OBD2 Pr...is design a controller that will act as the master of the interface. It will obtain the current status of the specified sensors, make a decision about them, and then issue some command to the secondary device. The controller will likely need to include an embedded processor. I need a software guy to write the code for the processor. 5.? ? ? ? ? ? The controller will be implemented either in an FPGA or in an ASIC, depending on cost. We will design a circuit board to mount the controller and to have connectors for the OBD and secondary device. Probably may also need power supplies and other devices (i.e. Flash memory for my processor code). Paul Girodo 604 266-8...

I need a small application that can communicate via USB with a Nexys II board (FPGA board). It has to write files into the board's RAM or Flash memory. A similar application already exists, but I need some extra features. ## Deliverables basically I need this application: (MemUtil) In my project I'm designing an wave player. The problem is that wave files are large, and I only have 16 + 16 MB of memory (RAM and ROM). MemUtil can only store a file at a time. So my application needs to divide a file into 16MB (or less) pieces and write them into memory between reading cycles (requires handshaking protocol). Extra feature: the application should be able to convert mp3 files into wave files. This feature is desired but

• Design in VHDL • Convolution • Correlation • Filtering • Implementation on an FPGA board

Need to create a mashup for very niche job board site. Will use one or all of the following APIs (depending on price): , , The mashup will be for a very specfic skill. For example the site will pull all jobs with the keyword "fpga". Users can then filter based on various parameters allowed by the API methods. If you can do the web design too, great. If not I'll outsource the GUI design.

I am currently doing a project of which Im building a central heating prototype. this is done using FPGA spartan 3 starter kit. and I need help with programming it in VHDL. I have done all the hardware and includued everything in the file, all I need is the VHDL codes, for LCD interfacing, and programming a digital thermostat I used in my daughterboard and many other features you will find described in the file attached with this. Please have a look at my propsal and let me know if you can do it. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. ## Platform FPGA spartan 3 starter Kit.

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Design of PCI based 12 channels A/D converter. - PCI + FPGA based - Low cost PCI and FPGA. - A/D based on ADS1282 from Texas Instruments is a must. (see technical description from their site). - Excellent FPGA design. - PCI based on Linux and Windows - PCI Free Licence. AT this stage of the design it is not required PCB design. FPGA design, and diagrams are required. Schematics and description of the modules are required. Low-cost is very important.

1. The board will attach to PC video card (DB-15 VGA) and act as a pass through to monitor. Board can disable video signal output to monitor using a simple mux circuit . The board will detect the frequency of the incoming video signal. Only 3 frequency will be counted 15Khz, 25Khz, 31Khz all else will be blanked. These frequencies can be set by on board jumpers. 2. When the VGA signal is blanked, the board will output a video signal of its own at a pre-selected fixed frequency based on the above jumper. The output will be a simple color low res image or can be just text. Possible video output generator CLPD (Altera MAX II). 3. Board will connect to PC via USB. Board will be a HID keyboard device. Board will have 48 pulled up I/O lines. Each I/O line will be mapped to a character from...

...playback. ? After you make this work (playing a single channel audio file from the dongle to the CODEC, you will receive phase II hardware: Audio flow is: Data from u-law file -> AT32 -> SDRAM buffer -> SSC Port -> Codec(s) The SSC port uses the TX Data, TX Clock, and TX Sync lines.? In the phase-1 hardware a single CODEC connects to these lines. ? In the phase II (16 Channel) hardware, a Xilinx FPGA U10 splits the data out into separate sequential streams for each of the 16 channels. We will pay 50% of the bid on completion of Phase-I, then we will send you phase-II hardware, which will look similar to this: [][5]. The current schematic of phase-II hardware is here: [][6]? This hardware has the 16 codecs and Xilinx. ? ? The

I require a logo designed for my Company "XenoSem Design Services" A Low-Cost Alternative for Your Next Hardware Design -The logo needs to reflect the area of work I am in, which is PCB design, FPGA design, ASIC design basically electronic hardware/board design services. -The artwork needs to be original. Please feel free to be creative -Would be great if the logo can reflect that XenoSem is a low cost alternative for board design -Will prefer designers who can send a sample of their earlier work for a similar type of design. -The logo needs to have the Complete Company Name. The tagline will be beneath the logo and need not be part of the logo. -Background, images should be strictly non-copyrighted -Feel free to experiment with colours, ...

... 1) PCI interface is based on FPGA 2) FPGA PCI-target core is FREE of license 3) FPGA has SPI-master core 4) FPGA has TDM interface 5) FPGA with lowest price is required! 6) PCI device must have usual interface for OS (Linux in most) - BAR, DevID, VendorID etc 7) PCI device must have 3-5V interface The structure of the PCI-card is a follows: FPGA <-> Infineon DuSlic-SP chip 8 wires are the interface to DuSLIC: a) 4 wires for SPI (CS, CLK, TX, RX) b) 4 wired for TDM (FS, CLK, TX, RX) Altera or Xilinx FPGAs are preferred, but not required. The lowest price is the main feature. No schematic for DuSLIC is in this project. Only PCI card + some connector for 8 wires. The PCB design for the card is not required. Sch...

...following requirements: 1) PCI interface is based on FPGA 2) FPGA PCI-target core is FREE of license 3) FPGA has SPI-master core 4) FPGA has TDM interface 5) FPGA with lowest price is required! 6) PCI device must have usual interface for OS (Linux in most) - BAR, DevID, VendorID etc 7) PCI device must have 3-5V interface The structure of the PCI-card is a follows: FPGA <-> Infineon DuSlic-SP chip 8 wires are the interface to DuSLIC: a) 4 wires for SPI (CS, CLK, TX, RX) b) 4 wired for TDM (FS, CLK, TX, RX) Altera or Xilinx FPGAs are preferred, but not required. The lowest price is the main feature. No schematic for DuSLIC is in this project. Only PCI card + some connector for 8 wires. The PCB design for the card is not required. Schematic +...

...and provide any additional features to make the vending machine as user friendly as possible (e.g. maybe using the LEDs or LCD in some way). --Target your design to a Xilinx Spartan-3 or Spartan-3E FPGA. Download to the starter board and demonstrate correct operation . look at deliverables... ## Deliverables --A structural design using a package and multiple components (total, display, change, serial, etc) is required. --Include simulation waveforms demonstrating the correct functional operation of your machine. Also include schematics of your synthesized design and include a summary of the FPGA resources used. --Project guidelines. Multiple Files You should create multiple files, one for each of your modules (, , , etc) and the top level file. Each

Hi all I'm having a trouble in chip design work. I want an program source code (in any programming language) that - Import any designs based on VHDL source code or netlist exported from Xilinx or Altera Development Tool (Quartus, ISE,...) - Parse and Implement any algorithm that will modify the design to give an new design which power consumpt is reduced - Certainly, output is the new power optimized netlist or VHDL source code that can be imported again to Quartus or ISE (xilinx). To prove that power consumption has been reduced in modified design, I will test base on power estimate tool of Quartus or ISE. Although these development tools have optimized power when synthesis but I want to do it myself. So you can use any algorthm that can optimize power such as RTL isolation, clock ga...

Description We have written a compiler that translates source code in a parallel language into logic equations suitable for loading in to a Field-Programmable Gate Array (FPGA). The nature of the source language is that separate processes could be compiled independently. These could then be run on separate FPGAs. I now need a simulator that can display the behaviour of each part of the circuit. I expect that this program will be written in Java and will use graphics to display the waveforms of the signals being monitored. We are using a number of tools to assist us, for instance the SableCC parser-generator. This might be useful in this project, too. References 1. The CPA2004 and PDPTA2005 papers at 2. SableCC

Implement a special efficient pipelined DDR-SDRAM controller into a Spartan 3 FPGA as described in the attached docuement ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment. b) For all others including desktop software or software the buyer intends to distribute: A software installation package that will install the software in ready-to-run condition on th...

Implement a special efficient pipelined DDR-SDRAM controller into a Spartan 3 FPGA - Pipeline (incl. bank switching) - Read a 64bit value - incremet and write back the 64 bit value to the same adress - during wait cycles on the one bank the same process should run on the other bank (alternating) - total 4 independant DDR-SDRAMs connected to the Spartan3 - SDRAM type: V58C2512164SAJ-5 - Spartan3: XC3S1500FG676 - speed: DDR SDRAM clock min 96 MHz, no "NOP" cycles in access - hardware already available We provide UCF-file and Verilog interfaces to our logic. If necessary we can provide an evaluation hardware. Expected deliverals: Xilinx ISE 9.1 project including well-documented Verilog sources and simulation We will check for proper operation.

...project should include the following: - encryption/decryption algorithm on fpga - interconnection block between 2 fpga's - communication block between computer and fpga fpga1 is connected to pc1 and fpga2 is connected to pc2. fpga1 and fpga2 are connected between them using ethernet, serial, usb (your choice) User1 sends from pc1 to fpga1 a plain text, fpga1 encrypts the text and send the cipher text to fpga2, fpga2 decrypts the cipher and send it to pc2, user2 receives the plain text. This is how these project should work. For the communication between boards i can give you another project like this one to take the block for board communication. I will also give you the terminal software for pc-fpga communication. You should implement th...

...project should include the following: - encryption/decryption algorithm on fpga - interconnection block between 2 fpga's - communication block between computer and fpga fpga1 is connected to pc1 and fpga2 is connected to pc2. fpga1 and fpga2 are connected between them using ethernet, serial, usb (your choice) User1 sends from pc1 to fpga1 a plain text, fpga1 encrypts the text and send the cipher text to fpga2, fpga2 decrypts the cipher and send it to pc2, user2 receives the plain text. This is how these project should work. For the communication between boards i can give you another project like this one to take the block for boad communication. I will also give you the terminal software for pc-fpga communication. You should implement the...

The coder must implement a chaotic encryption algorithm on a Xilinx Spartan 3 FPGA. I will provide the chaotic algorithm. Also, suggested chaotic algorithms are welcomed. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment. b) For all others including desktop software or software the buyer intends to distribute: A software installation package that will inst...

I need somebody to quickly translate 550 lines (includes comments) of Verilog code to VHDL. The code is for a state machine and has no complicated constructs. Comments must be conserved and signal names will need to be prefixed with s_, variable names with v_, input ports with i_, output ports with p_, etc. The resulti...platform(s) specified in this bid request. 3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement). ## Platform Any of the free fpga (Altera, Xilinx, Lattice) tools can...

...to complete your goals within the allotted time. design should be simulated using Xilinx ISE software and input using schematic capture. specified and thorough test bench waveforms will be used to simulate your design. and placement issues should also be given due consideration. time allows, you will download your design files to a Xilinx Spartan 3 based, FPGA development board and demonstrate the operation of your design. Your design should therefore consider the hardware limitations of the prototype board. 9.A technical report of a standard formal style will be required to be submitted, which should include: a.Introduction. design & reasons for choice. circuit design methodology, including considerations of BIST/JTAG if included

The project has to be done in P-CAD 2001. I will supply used component library, old and new P-CAD schematics, current P-CAD PCB, list of changes. The basic layout stays the same. Few minor components have to be created and added, some removed. The FPGA component has errors in pin designation. I have created a good one, which has to be used instead. The FPGA inputs/outputs have to be redesignated according to the board layout, some power pins have to be moved. DRC (Design Rule Check) and (ERC Electrical Rule Check) have to be performed and return no errors. Silk screening has to be done in a reasonable fashion. As a result of your work I need a P-CAD schematic and a P-CAD PCB files matching each other with an according component library. I don't need Gerber files...

c code for a photo realistic ray tracer. the code must be stand alone and also have a full windows gui. the code should also be made in parallel integer such as would be of use as input to the mentor graphics pfogram "cataplut c" for the conversion of the code to fpga. Only people familiar with parallel integer c code need apply

Need info on FPGA packages

My project is a curriculum based project which needs to be completed within 2 months from today.? So if i get a good help from anyone who has worked already will be greatly helpful to me. ## Deliverables Rent A Coder requirements notice: As originally posted, this bid request does not have complete details. Should a dispute arise and this project go into arbitration "as is", the...will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement). ## Platform os: any above 98 environment; using xilinx ise6.0 or hi...

I require a (Altera)NIOS II, CPU processor to be enhanced, i require the interrupt controller to support 32 UARTS and Interrupts from Timers,EPCS and the LAN. Ideally i require the system to have 36-38 Interrupts. Requirements. VHDL source for new Interrupt Controller Details of how to integrate into NIOS II and Quartus Example C Source for Setup of new c...on the platform(s) specified in this bid request. 3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement). ## Platform FPGA...

I'm looking to build a relationship with a few coders for various bits of work - web (LAMP based - Perl/PHP, AJAX etc - all the corportate buzzwords) as well as web GUI design, video processing (C++ or similar), firmware (PIC family assembler), FPGA development (VHDL and Altera QuartusII visual code) and so on. This is a trial project to see how you work in the area of video processing in a windows/linux PC environment. It is quite simple, but I have been told that I need to sort out the quality of coders on here. This particular project: Unit 1: - Take a number of MPEG video files, and break them down frame by frame into audio and video (e.g single picture frames and 1/25 sec audio slices). - Digest each frame+audio into a number of separate 1-byte fingerprints (e.g. average H...

Hello, I am looking to implement a deciphering algorithm to place on a network monitoring board. I'll need some form of report which tells me how all this can be done, and an estimate of work effort. Bidders must have proven experience with implementing FPGA's for telecommunictaions work. Details of the FPGS board are below http://w...on the platform(s) specified in this bid request. 3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement). ## Platform FPGA

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Circuit design for Lattice CPLD/MachXO. VHDL or Verilog. Interface to the Netburner processor module (see MOD5282). Timers. Encoders input processing. Counters. Pulse Width measurement. Ouput Compare Triggers. 32Bit Multiply and Shift operations. State Machine. We will submit more details upon acceptance. Duration 30 Days max. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's ...

I need a website for my company. My company is an embedded software development company called Yankee Bush Software LLC. We specialize in programming services for C, C++, Assembly, RTOS, Matlab, Simulink, FPGA Design, DSP's, VHDL, Verilog, and Device Drivers. I have a website already called [][1]. I don't like it. Its mostly shopping cart software. I like the site called <> ; I'd like someone to create a site like this one for my company. Note: I'm not going to use shopping cart software anymore. There's no need for it. I can't update my old site either. It will have to be all new code. I'm trying to get my company to stand out. When someone goes onto my site. I will give you more details about my company and any other information

This project is a concept-proof stage of a larger project and I would prefer if winning bidder would be interested to receive invitations to bid on next stages. The project involves a creation of stand-alone scan ramp generator, based on FPGA DSP, for use in charged particle beam systems. At this time only bids for a concept-proof stage of a project are solicited; concept-proof stage is intended to demonstrate programmer's ability to handle the task and also technical feasilbility of a concept. Detailed requirements for a concept-proof design are included in the attached file and any additional technical questions are welcomed. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliv...

My final year thesis is to interface dirctly the CMOS colour image sensor OV7620 (omnivision) to the DSP TMS320C6711. The problem is that the sensor is controlled by the I2C I want to do so without the use of an FPGA, i must implent the I2C protocol in C Language for the specific DSP. I think that an option is to program McBSP channels to act as GPIO (an example is from texas instruments), where i think to implement the I2C. I need the code be fully fuctional for I2C transition from the sensor. If you need more aplications notes will be in touch. If it is possible there is a need for the ccs files and details about RAM initialization,EMIF and EDMA usage. ## Deliverables Rent A Coder requirements notice: As originally posted, this bid request does not have complete details

I need to develop a device based on FPGA altera or xilinx capable of getting data from the net and display my data into vga screen This is an FPGA project

We need for a motion control project numerous hardware functions to be implemented into an FPGA. Functions include PWM generators, SPI interface, quadrature encoder, pulse capture and width measurement. Code to be written in Verilog. Full job specification to be released in 60 days. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment. b) For all...