As an RTL Design Engineer with significant experience in both Front-end and Back-end Digital IC Design, I possess a robust and extensive understanding of Microelectronics, specifically in Digital IC Design. I've contributed to constructing various components of Digital Baseband Processors and have expertise in AI Accelerator Design. My skill set includes proficient use of Verilog, TCL Scripting, C/C++ Programming, MATLAB, ModelSim, Xilinx Vivado, Mentor Graphics (Pyxis), Cadence (Virtuoso, Genus, Xcelium) and Synopsys (VCS, SDC, Astro, PrimeTime)