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    706 altera de2 nios qsys jobs found, pricing in USD
    FPGA replacement on Control Board - Prototype Phase Ended

    I'm looking for an individual with expertise in Altium Designer. This project involves replacing an obsolete Xilinx FPGA with an Altera part. The initial project has been done in Altium Designer. ECAD would need to be done in Altium 19.

    Circuit Design Electronics PCB Layout
    $161 (Avg Bid)
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    Custom FPGA Logic Wizard Needed Ended

    ...freelancer with expertise in FPGA coding to bring a custom logic design project to life in Noida (Delhi/NCR). **Project Objectives:** - Development and implementation of custom logic designs using FPGA. - Ensuring designs are efficient, reliable, and meet project requirements. **Skills and Experience:** - Strong background in FPGA programming and design, with specific experience in either Xilinx, Altera, or Lattice platforms preferred. - Proven ability to develop and optimize custom logic designs. - Excellent problem-solving skills and creativity in designing unique solutions. - Ability to work independently and deliver project milestones on time. **Application Requirements:** - convert LVDS signals to MIPI CSI2. - preferably using Lattice crosslink. This project offers an ex...

    DDR3 (PCIe, board design/fpga) Electronics FPGA FPGA Coding Verilog / VHDL
    $380 (Avg Bid)
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    Crossing road Game using de2-115 Ended

    I am looking for an experienced developer to create an FPGA-based game similar to a classic crossing road game with a twist. Required Skills: - Proficient in VHDL programming - Experience with FPGA design and implementation - Familiar with character movement logic - Ability to implement a scoring system into FPGA projects Project Requirements: - Design VHDL code specifically for an FPGA target device - Develop code that allows character movement within the game - Create a scoring system to track and display the player's score -able to score to reach a target and gameover point -able to control the game using fpga or keyboard - able to connect via vga Ideal Candidate: - You should have a portfolio demonstrating previous work with FPGAs and VHDL. - Experience in game development or...

    Electrical Engineering Electronics FPGA Matlab and Mathematica Verilog / VHDL
    $146 (Avg Bid)
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    FPGA UART Interface Expert Ended

    I'm seeking a talented individual with a strong background in VHDL and FPGA design, specifically with Altera products, who can successfully implement communication interfaces within my project. The ideal candidate will possess a deep understanding of UART protocol and be capable of integrating it with other interfaces. Requirements: - Proficiency in VHDL programming for FPGA - Experience with Altera FPGA design tools - Successful implementation of UART interfaces - Knowledge in LAN and USB communication The scope of the project includes: - Implementing a low-speed UART interface (up to 115200 bps) - Integrating UART with LAN and USB interfaces on the FPGA The right freelancer will have a strong portfolio demonstrating their expertise in FPGA interface design and commu...

    Electrical Engineering Electronics FPGA Verilog / VHDL
    $520 (Avg Bid)
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    FPGA Function Generator Ended

    I am looking to hire a freelancer to design an FPGA function generator using a Altera MAX 10 FPGA, 10M08SAE144C8G that produces a frequency of 10 MHz and above. The desired waveforms are sine, square, and triangle. This function generator should also have a single channel. If you think you have the skills to help me with this project, feel free to bid on it. Thank you!

    Electrical Engineering Electronics FPGA Matlab and Mathematica Verilog / VHDL
    $112 (Avg Bid)
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    fpga programming Ended

    My project is about FPGA programming for control systems. I'm using the Altera Cyclone V board and the preferred programming language is Verilog. This project requires someone with experience in FPGA programming and the design of embedded systems. The programmer should be able to develop design flows for FPGA devices, debug them and modify existing designs for better performance. The knowledge of hardware description languages such as VHDL and Verilog is crucial, as they will be used for implementation and testing of the designs. Additionally, some knowledge of microcontrollers and communication protocols will be required. The right person for this job should have strong problem-solving skills, excellent coding and debugging capabilities, and a deep understanding of hardware in...

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    $167 (Avg Bid)
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    22 bids
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    Help me with altera de0 board Ended

    Project Title: Altera DE0 Board Programming Assistance Description: I am seeking a freelancer who can provide programming assistance for my Altera DE0 board project. I require expertise in VHDL programming language and the ability to modify existing code as well as start from scratch. Skills and Experience: The ideal candidate for this project should have: - Proficiency in VHDL programming language - Experience with Altera DE0 board - Strong troubleshooting and debugging skills - Knowledge of hardware design consultation Specific requirements: - Provide programming assistance for the Altera DE0 board - Modify existing code and develop new code from scratch - Troubleshoot and debug any issues that arise during the programming process - Provide hardware design ...

    C Programming Electronics FPGA Microcontroller Verilog / VHDL
    $36 (Avg Bid)
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    FPGA interfacing with AFE and sub systems Ended

    Hello,I am looking for devs who has experience and knowledge in FPGA to interface RF AFE chip from analogue device(exact part number via chat) Desired FPGA- xilinx Zynq/ equivalent series, Cyclone/equivalent from altera. The FPGA will be interfaced with the AFE and will act as an DSP. Apart from the AFE the FPGA is expected t be interfaced with: 1) Display module 2) Keypad 3) Memory 4) Microphone 5) ESP32C3 and GNSS module. Additional MCU/processor can be added to reduce the burden on FPGA. It can be decided after discussing. The FPGA will perform the DSP task and will be used to transmit RF waveforms. It will be used to perform frequency hopping and encryption (AES-256/SHA) task for the waveform. More detailed information via chat. Eligibility: The freelancer must have...

    Electrical Engineering Electronics Embedded Systems FPGA Verilog / VHDL
    $644 (Avg Bid)
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    EE Engineer for the smart bottle Ended

    I am an EE engineer. I have lots of experience designing both analog and dig...C/C++ (both procedural and OOP). *for STM and nrf controllers Mbed OS could be one of the choices for programming the MCU. I have done lots of projects in the field of wireless communication and IoT using different wireless communication protocols like BLE, RF, WiFi (Cloud), etc. In the field of bit streaming, high-speed processing and ML, I am able to program both Xilinx and Altera in VHDL or C/C++ for Microblaze or NIOS II processors. For manufacturing purposes, I can provide component selection and BOM which suits your needs for a durable, efficient, and effective design. ABOUT YOUR PROJECT, I have done lots of similar projects before and can handle your project easily. We may discuss it more o...

    C Programming Electrical Engineering Electronics Microcontroller PCB Layout
    $1860 (Avg Bid)
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    Design and Implementation of an ‘Autonomous Self-Navigating Robot’ Ended

    ...developing co-design projects. There are many possible solutions to the design problems depending on the way in which you choose to partition each problem. HW/SW Specs: The target embedded systems platform can be either the AlteraDE0 FPGA platform or the PSOC. Both devices/boards provide the opportunity to implement low-level, interrupt driven, device drivers along with the custom hardware. Altera DE0 Board: This board has a Cyclone III FPGA fitted. This supports a ’soft-core’ processor integrated with custom hardware. Using the Nios2 softcore CPU as a base you will implement a system to control a robot arm. There is the potential to use a small embedded O/S, FreeRTOS, uCLinux, or to write your own scheduler for this solution. PSoC: PSoC is industry&rsqu...

    Electrical Engineering Electronics FPGA FPGA Coding RTOS
    $276 (Avg Bid)
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    debug FPGA program - Cyclone Altera chip Ended

    I have a board i need to fix for an equipment in my store. Looking for an FPGA expert that can debug the program files i got from the manufacturer. I was told this should be simple for someone that knows what they are doing.

    Arduino Electronics FPGA Microcontroller Verilog / VHDL
    $151 (Avg Bid)
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    fpga video processing pipeline. -- 2 Ended

    ...filters (like hq2x) 4. output from scaler is passed through optional scaline generator, where scanline parameters are passed as input wires : scanline color, scanline thickness, scanline interval 5. output is overlayed by the bitmap OSD with the same resolution as output format Requirements : aside from the DDR memory interface, or PLL no vendor or encrypted IP blocks can be used, for example no Altera/Intel video pipeline. Everything must be in written verilog source code. Must include verilog testbench that will accept input picture(in any format) and produce resulting picture(in any format). suggested pipeline i/o ports: Sysclk, [23:0] RGBin, HSin,VSin,DEin, Clkin [23:0] RGBout, HSout, VSout, DEout, Clkout [31:0] parameters[0:...] (whatever count is required). all needed m...

    Electronics FPGA Verilog / VHDL
    $2000 (Avg Bid)
    NDA
    $2000 Avg Bid
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    XTEA Light Encryption-Decryption Engine Ended

    In this project students are asked to implement a an XTEA Encryption/Decryption VHDL Engine, implemented in both C code and VHDL code. It supposed to be built as a custom hardware module and be interfaced to the NIOS II soft processor in the Alter- Intel Cyclone V FPGA chip [De-10Nano board]. The HDL code implements 2 number of pins: first an input from stdr_logic_vector type form of 32-bit length, and second an output with 32-bit of the same type. The Key is 32-bit in length, and they must be stored inside the VHDL code. The input reception and output generation may take multiple clock cycles or states but could be designed in less than that if was applicable. The internet could be surfed to lookup codes for both C and VHDL but the group is responsible to convert and modify the cod...

    C Programming C++ Programming Electronics Microcontroller Verilog / VHDL
    $492 (Avg Bid)
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    Debugging VHDL code for Nios Processor Ended

    Hi Moaz Khaled Feriz K., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

    Altera Quartus ASIC Digital ASIC Coding FPGA Verilog / VHDL
    $35 / hr (Avg Bid)
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    Need to convert MATLAB code to synthesizable VHDL code Ended

    Need to convert MATLAB code to synthesizable VHDL code. I am using DE2 FPGA board for testing

    Electrical Engineering FPGA LabVIEW Matlab and Mathematica Verilog / VHDL
    $80 (Avg Bid)
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    Convert MATLAB code to VHDL code Ended

    Need to Convert MATLAB code to VHDL code. I Have a MATLAB code i want someone who can convert that code to a sytnthesizable VHDL code for ALtera FPGA.

    Electrical Engineering FPGA LabVIEW Matlab and Mathematica Verilog / VHDL
    $75 (Avg Bid)
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    class 12th maths nios , cbse Ended

    I am looking for maths tutors

    Math Tutoring Mathematics
    $12 (Avg Bid)
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    24 bids
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    i 10 nios car modeling -- 2 Ended

    I want a grand i10 nios car design in 3d model Maya file project file

    3D Animation 3D Modelling 3D Rendering 3ds Max Maya
    $25 / hr (Avg Bid)
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    FPGA Altera implementation Ended

    Implement the circuit design in the FPGA, and read input /write output to the file. Including timing analysis, power consumption and pin planner etc... Using Quartus prime

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    $507 (Avg Bid)
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    BPSK demodulation using fpga Ended

    I m looking for a fpga design for an BPSK demodulator, the fpga ill be using is altera, i ll also require an simulink file illustrating the functionality of the demodulator, i provide the input file for the demodulator.

    Electrical Engineering FPGA Coding Matlab and Mathematica Verilog / VHDL
    $193 (Avg Bid)
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    Write VHDL code and Testbench to find shortest distance between two points (Note : use Dijkstra's Algorithm) Ended

    Write VHDL code and testbench for the given question and simulate them using Quartus and Modelsim Altera

    Verilog / VHDL
    $19 (Avg Bid)
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    Quartus ALTERA project Ended

    Design a fully digital, hardware-based direction discrimination and counting system for use with quadrature encoder-based rotatory incremental encoders.

    Altera Quartus Electrical Engineering Electronics FPGA Verilog / VHDL
    $171 (Avg Bid)
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    i 10 nios car modeling Ended

    hello I want a grand i10nios car in 3d model in the Autodesk Maya file project

    3D Animation 3D Modelling 3D Rendering 3ds Max Maya
    $15 (Avg Bid)
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    car modeling Ended

    hello i need to grand i10 nios car 3d model in the Autodesk Maya file project

    3D Animation 3D Modelling 3D Rendering 3ds Max Maya
    $2 / hr (Avg Bid)
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    I need VHDL Designer Ended

    This is a final year project. We are struck with simulation. Need to debug our program, or else develop the project from scratch. I am attaching the code that we have wrote for your reference. We used Quartus altera for coding, and model sim for simulation. The development board is a cyclone 2. There were no errors as such. The code would simulate and after one clock cycle, the output would become 'Z'. From what I understood, the main issue is the interconnection between all the modules.

    Electronics FPGA Microcontroller Verilog / VHDL
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    Fractal image compression in vhdl Ended

    hi everyone, I need a fractal image compression code (for a 128*128 image) implemented on a DE2 cyclone II in the M4K memory which has 105 blocks.

    Electrical Engineering FPGA Image Processing Verilog / VHDL
    $143 (Avg Bid)
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    Video transiver over ethernt de2-115 Ended

    Hello, I need design video transivver use de2-115 FPGA use SystemVerilog, ethernet and usb camera Rettru Mini HD 1080P. Video must be encrypted aes-256. De2-115 need recive command over ethernet for start/stop with host verification.

    Digital Design FPGA Verilog / VHDL Video Broadcasting
    $750 (Avg Bid)
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    Send Automatic Whatsapp Message every sell ( my ERP have API ) Ended

    Hello. I have a sales system (ERP) that has an open API. I need and a BOT/System that whenever a sale happens, the bot sends a message to my client via whatsapp. System API is very complete. The API notifies you when there is a sale, the API has all the customer's data such as Phone number, Name, Address, emai...thank you message, with order information (information is available in the API) Bot need use my own mobile number... Invoice API: Order API: Callback Status order: ( portuguese, translate to your language )

    C Programming JavaScript MySQL PHP
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    Altera De1 SoC FPGA Ended

    Write a program using QUARTUS ALTERA to work on De1-SoC FPGA BOARD. .................. The LED Brightening Control with an Absolute Encoder The circuit to be designed must provide control of the brightness of a single or multiple LED ‘s using values from an Absolute Contacting Encoder (128 positions). In addition, the circuit must display a decimal value of the LED intensity (0-127) by using three seven-segment displays. The circuit contains four logic blocks and 3 external components (Figure 1). The logic circuits are: • Code Conversion Table • Binary to BCD 3 digits (Decimal Values) • LED Brightening Control (PWM) • Seven Segments Decoder

    Altera Quartus Electronics FPGA Verilog / VHDL
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    Traffic Control System Ended

    Traffic Control System (Two intersection road) using VHDL in Quartus II. Write Code, test bench and simulate in Modelsim Altera. Draw Flow diagram or ASM chart and Mnemonic document state diagram.

    Electronics Engineering FPGA Microcontroller Verilog / VHDL
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    VHDL project 'Analog to digital converter' By using a sensor for FPGA kit. Ended

    In this project I want to see how the ADC works in FPGA kit .. with any sensor LED or temp. The board is ALTERA Cyclone IV EP4CE6e22cb

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    $15 (Avg Bid)
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    Need a computer science tutor for practicals Ended

    Need help in completing this NIOS Practicals

    C++ Programming HTML MySQL
    $16 (Avg Bid)
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    HPS DE10 Nano support Ended

    Hello, I’ve just received my DE10-Nano board and I’ve already created a project in VHDL, Qsys and application level code in *.c (simple LED). I already know how to create the *.rbf, the preloaded file, the and all the file necessary to boot out of the uSD card. I already have an installation for the Quartus (18.1), SOC EDS and Putty. What I don’t know is how to write every thing into the uSD card partitions and to run a complete simple LED code. Can anybody help me to complete a that ~5% that I have left for fully SOC code? *A preference is to those who have a the DE10 board. Idan

    C Programming Linux SoC Design Verilog / VHDL
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    Quartus Altera/INTEL Ended

    Looking for a tutor on Quartus Altera/Intel MAX10 FPGA device. Knowledge of QSYS, Platform designer, Eclipse, HDL/VHDL. Embedded system control design using FPGA. Closed loop control ADC sampling, PI controller , PWM generation in HDL/VHDL.

    Altera Quartus Digital Signal Processing FPGA Microcontroller Verilog / VHDL
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    Content writing for website Power electronics converter battery charging. Ended

    Looking for website content for Power electronics converter for battery chargers for EV market. Magnetics design , Embedded software FPGA. Altera/Intel VHDL.

    Content Marketing Content Writing Electronics Power Converters Website Design
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    VHDL SD card implementation Ended

    Hello, In my project I need to store data on my FPGA Altera EVMs. The data must be stored on a non-volatile device (power done can occur at all time). To do that, I need to implement an interface to the on board uSD card. Here are some specification: 1. SD Card: Class 10, 2GB. 2. Min write speed: 200Byte every 1ms (effective) ~1.6Mbps. 3. Read speed: 10Mbps (Flash all mode) 4. All VHDL (NiosII- only when guaranteed performance). 5. Full Duplex- Optional. 6. Target: DE10-Nano and DE2-115. 7. Delete all data function: optional. Thanks, Idan

    FPGA Verilog / VHDL
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    Project for Worldfast Translator24 Ended

    Hyundai smallest SUV Casper (AX1) coming in global & Indian market _ Hyundai Casper will be smaller than Hyundai Venue _ Casper could be based on K1 platform from new santro & Grand i10 Nios _ Casper is expected to get 2 engine options; a 1.2 litre petrol from Grand i10 Nios & for lower variants a 1.1 litre petrol engine _ It could get Venue's 1.0 turbo petrol in some markets _ Hyundai Casper global unveil is expected in September 2021 & It will be first launched in Korea, then in India _ ? What are your thoughts on Hyundai smallest SUV Casper? _ ? Will you choose this over Maruti Suzuki Ignis, Mahindra KUV100 & Upcoming Tata HBX ?

    English (UK) Translator English (US) Translator Korean Translator Spanish Translator Translation
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    Digital electronic -- 2 Ended

    You are required to design and implement a state machine based control system for a car barrier system. It will be required to take simulated inputs from sensors that detects the presence of a car and requires a coded entry system. It must suitably control the barrier and lights to allow safe progress of the car. This must be implemented as a fully functioning desig...design and implement a state machine based control system for a car barrier system. It will be required to take simulated inputs from sensors that detects the presence of a car and requires a coded entry system. It must suitably control the barrier and lights to allow safe progress of the car. This must be implemented as a fully functioning design verified by simulation and can be demonstrated on the DE2-115 developmen...

    Circuit Design Electrical Engineering Electronics Engineering PCB Layout
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    Electronic Ended

    ...design and implement a state machine based control system for a car barrier system. It will be required to take simulated inputs from sensors that detects the presence of a car and requires a coded entry system It must suitably control the barrier and lights to allow safe progress of the car. This must be implemented as a fully functioning design verified by simulation and can be demonstrated on the DE2-115 development boards A detailed brief is given at the end of this document. The deliverables required from this assessment are: This design report must detail the functionality and operation of your state machine. It should contain a state diagram and an explanation of how this meets the functional requirements of the specified problem. It should also provide details ...

    Circuit Design Electrical Engineering Electronics Engineering Verilog / VHDL
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    Digital electronic Ended

    You are required to design and implement a state machine based control system for a car barrier system. It will be required to take simulated inputs from sensors that detects the presence of a car and requires a coded entry system. It must suitably control the barrier and lights to allow safe progress of the car. This must be implemented as a fully functioning desig...design and implement a state machine based control system for a car barrier system. It will be required to take simulated inputs from sensors that detects the presence of a car and requires a coded entry system. It must suitably control the barrier and lights to allow safe progress of the car. This must be implemented as a fully functioning design verified by simulation and can be demonstrated on the DE2-115 developmen...

    Circuit Design Electrical Engineering Electronics Engineering PCB Layout
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    FPGA I2C module Ended

    prepare a I2C module for Altera FPGA

    Electrical Engineering Verilog / VHDL
    $156 (Avg Bid)
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    VHDL simple set of PROJECTs to simulate Ended

    VHDL , QUARTUS , MODELSIM ALTERA, QUESTASIM, UP DOWN COUNTER , COUNT ZERO COUNTER, CLOCK GENERATOR, RGB CONTROLLER. STATE MACHINE ...

    Circuit Design FPGA FPGA Coding Verilog / VHDL
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    Quartus 2019.1 Project development Ended

    Hello All, I need to develop a project with Quartus 2019.1 software tool. I need to create a schematic based design approach for DE2-115 evaluation module. Hardly 2Hour job. Please bid if you're completely aware of the design flow with Quartus 2019.1 software. Having DE2-115 evaluation module will be added advantage.

    FPGA FPGA Coding Verilog / VHDL
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    INTERFACE a ADC with TERASIC DE4 board Ended

    The AD 9254 is to be interfaced with TERASIC DE4(Altera startix IV) in DSP builder platform

    Electrical Engineering Electronics FPGA MATLAB Verilog / VHDL
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    Altera Quartus II Computer Aided Design Software and Modelsim-Altera Simulation Software Ended

    Hi I need an expert in these two software Altera Quartus II Computer Aided Design Software and Modelsim-Altera Simulation Software. inbox me for more details.

    Altera Quartus Electrical Engineering Engineering
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    Keypad 4X4 VHDL decoder Using VHDL: ModelSim altera/ Quartus/ Questasim Ended

    1. Encode key presses on a standard 16-key 2. give a stable 4-bit binary output 3. Have output to indicate when a key is being pressed.

    Circuit Design Electronics FPGA Microcontroller Verilog / VHDL
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    Create me a VHDL ping pong game using FPGA that has 1 player against computer, 2 players and 2 players against computer Ended

    VHDL, DE2 Board 115, Ping pong game, max score is 16 and the ball speed should increase when the score is 10 and the ball color as well

    FPGA Verilog / VHDL
    $100 (Avg Bid)
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    Create me a VHDL ping pong game using FPGA that has 1 player against computer, 2 players and 2 players against computer Ended

    VHDL, DE2 Board 115, Ping pong game, max score is 16 and the ball speed should increase when the score is 10 and the ball color as well

    Electrical Engineering Electronics FPGA Microcontroller Verilog / VHDL
    $161 (Avg Bid)
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    Quran reader Ended

    i need an mobile App . like house of Quran but i need it on mobile . with extra requirements.

    Android iPad iPhone Mobile App Development
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    DDR3 layout in Altium Ended

    Dissolve DDR3, FlyBy topology, 2 Altera SoC chips. 8 layers (S-P-P-S-S-P-P-S), 3 (4, 5, 8 layers) available for DDR wiring. Changing the placement of components is acceptable if critical. Alignment rules and signal classes are defined. Deadline until 28.02. It is possible to expand the order to a complete layout of the board with an increase in cost and extension of terms.

    Circuit Design Electrical Engineering Electronics Microcontroller PCB Layout
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    $30 - $250
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