Advanced Verilog Coding for HDL -- 3

I am looking for an experienced Verilog developer who can work on my Verilo HDL project. Design a digital circuit for a fruit sorter based on following specification. Develop the block diagram (consists of datapath and control units) and the ASMD chart. Assume that there is a 1-bit RESET signal to reset the circuit and it is asynchronous and active low. In addition, there is a 1-bit CLOCK as the clock. The circuit will start the operation when a 1-bit input signal START is asserted. A fruit detector provides a 1-bit input FRUIT that becomes 1 for one clock cycle if banana is detected and the FRUIT signal will be 1 for two clock cycles if orange is detected. There are 2 different outputs which are OUT1 and OUT2 that will be 1 for one clock cycle for the type of fruit where the total count is 3. OUT1 is for banana and OUT2 is for orange. Assume that the FRUIT signal is available at every three clock cycles. In addition, for the type of fruit where the output is become 1 for one clock cycle, the total count will be reset to 0 and the circuit can process the new input. Kindly refer to Figure 1 for an example of the simulation results. Submit following files to me through e-learning a. Verilog Modules (Design and Test Bench) [in .v format] b. Block Diagram and ASMD Chart [in .pdf format] c. Simulations results in waveform [in .pdf form